Semiconductor memory device including reset control circuit

ABSTRACT

A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a precharge operation in response to the reset entry signal and a refresh operation in response to the reset exit signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/528,642 filed on Sep. 28, 2006, which claims priority of Koreanpatent application numbers 10-2005-0090914 and 10-2006-0049002, filed inthe Korean Patent Office on Sep. 29, 2005 and on May 30, 2006, which isincorporated by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device, and moreparticularly to a semiconductor memory device providing reliableoperation.

DESCRIPTION OF RELATED ART

A system including a dynamic random access memory (DRAM) is reset whenits operation has an error. The system cuts off and reapplies power tothe DRAM during a reset operation. After applying the power, apredetermined delay is required for the DRAM to recover its normalfunction. Some DRAMs such as DDR3 DRAM include a reset pin for receivinga reset signal for resetting the system. In this case, the power iscontinuously supplied to the DRAM although the system is in a resetstate and, therefore, it is possible to reduce the predetermined delay.

FIG. 1 is a block diagram of a conventional command generator for use ina semiconductor memory device.

The command generator includes an input buffer 10, a command decoder 20,a row address strobe (RAS) signal generator 30, and a self prechargeunit 40. The input buffer 10 receives external control signals /RASand/CAS in synchronism with a clock CLK. The command decoder 20 decodesoutputs of the input buffer 10 and generates an active signal RACTP, arefresh signal REFP, and a precharge signal PCGP. The self prechargeunit 40 outputs a self precharge enable signal SPCG based on the refreshsignal REFP. The RAS signal generator 30, receiving the outputs RACTP,REFP, and PCGP of the command decoder 20 and the self precharge enablesignal SPCG, generates an active state signal OUT. The active statesignal OUT is activated when the DRAM is in an active state. That is,the active state signal OUT is active when the active signal RACTP orthe refresh signal REFP is activated. The active state signal OUT isinactivated when the precharge signal PCGP is activated. Further, theactive state signal OUT is inactivated in response to the self prechargeenable signal SPCG, which is activated after a predetermined delay addedto activation of the refresh signal REFP.

The command generator shown in FIG. 1 generates the active state signalOUT without regard to a reset signal. Meanwhile, the system enters andexits to or from the reset state without regard to an operation state ofthe DRAM. If the system enters the reset state when the DRAM is in theactive state, the DRAM can not receive any valid commands and is stuckin the active state. In this case, the DRAM is not able to perform itsfunction even after the system exits from the reset state. Thus, it isrequired for the DRAM to be reset when the system is in the reset state.

SUMMARY OF THE INVENTION

Embodiments of the present invention are directed to a semiconductormemory device including a reset control circuit for controlling itsoperation in response to a reset operation of a system using thesemiconductor memory device.

In accordance with an aspect of the present invention, a semiconductormemory device includes: a reset signal generator for generating a resetentry signal and a reset exit signal respectively in response to a starttiming and a termination timing of a reset operation of the system; anda reset controller for performing a precharge operation in response tothe reset entry signal and outputting a refresh operation in response tothe reset exit signal.

In accordance with another aspect of the present invention, asemiconductor memory device includes: a command decoder for decodinginput commands; a control signal generator for generating controlsignals for a data access based on outputs of the command decoder; and areset block for preventing the data access and performing a prechargeoperation and a refresh operation in response to a reset signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention willbecome apparent from the following description of preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a conventional command generator for use ina semiconductor memory device;

FIG. 2 is a block diagram of a command generator in accordance with anembodiment of the present invention;

FIG. 3 is a schematic circuit diagram of a reset state signal generatorshown in FIG. 2; and

FIGS. 4A and 4B are schematic circuit diagrams of a reset controllershown in FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a semiconductor memory device in accordance with thepresent invention will be described in detail referring to theaccompanying drawings.

FIG. 2 is a block diagram describing a command generator in accordancewith an embodiment of the present invention.

The command decoder includes an input buffer 100, a command decoder 200,a row address strobe (RAS) signal generator 300, a self precharge unit400, a reset input buffer 500, a reset state signal generator 600, and areset controller 700. The input buffer 100 receives external controlsignals /RAS and/CAS in synchronism with a clock CLK. The commanddecoder 200 decodes outputs of the input buffer 100 and generates anactive signal RACTP, an initial refresh signal REFPS, and an initialprecharge signal PCGPS. The reset input buffer 500 receives a resetsignal /RESET and outputs an initial reset control signal RSTB. Thereset state signal generator 600 generates a reset entry signalRST_ENTRYP and a reset exit signal RST_EXITP based on the initial resetcontrol signal RSTB. The reset entry signal RST_ENTRYP and the resetexit signal RST_EXITP respectively has information about a reset starttiming and a reset termination timing of a system using thesemiconductor memory device. The reset controller 700 receiving theinitial refresh signal REFPS and the initial precharge signal PCGPSoutputs a refresh signal REFP and a precharge signal PCGP in response tothe reset entry signal RST_ENTRYP and the reset exit signal RST_EXITP.The self precharge unit 400 outputs a self precharge enable signal SPCGbased on the refresh signal REFP. The RAS signal generator 300 receivingthe active signal RACTP, the refresh signal REFP, the precharge PCGP,and the self precharge enable signal SPCG generates an active statesignal OUT.

FIG. 3 is a schematic circuit diagram depicting the reset state signalgenerator shown in FIG. 2.

The reset state signal generator 600 includes a reset entry signalgenerator 620 and a reset exit signal generator 640. The reset entrysignal generator 620 includes three inverters INV1 to INV3, a first NANDgate NAND1, and a first delay DELAY1. The first inverter INVL invertsthe initial reset control signal RSTB. The first delay DELAY1 delays aninverted initial reset control signal output from the first inverterINV1. The second inverter INV2 inverts an output of the first delayDELAY1. The first NAND gate NAND1 logically combines the invertedinitial reset control signal RSTB and an output of the second inverterINV2. The third inverter INV3 inverts an output of the first NAND gateNAND1 as the reset entry signal RST_ENTRYP. The reset exit signalgenerator 640 includes two inverters INV4 and INV5, a second delayDELAY2, and a second NAND gate NAND2. The second delay DELAY2 delays theinitial reset control signal RSTB. The fourth inverter INV4 inverts anoutput of the second delay DELAY2. The second NAND gate NAND2 logicallycombines the initial reset control signal RSTB and an output of thefourth inverter INV4. The fifth inverter inverts an output of the secondNAND gate NAND2 and outputs as the reset exit signal RST_EXITP.

FIGS. 4A and 4B are schematic circuit diagrams showing the resetcontroller shown in FIG. 2.

The reset controller 700 includes a precharge signal generator 700Ashown in FIG. 4A and a refresh signal generator 700B shown in FIG. 4B.The precharge signal generator 700A includes a first NOR gate NOR1 and asixth inverter INV6. The first NOR gate NOR1 logically combines thereset entry signal RST_ENTRYP and the initial precharge signal PCGPS.The sixth inverter INV6 inverts an output of the first NOR gate NOR1 andoutputs the precharge signal PCGP. The precharge signal PCGP isactivated in response to an activation of the reset entry signalRST_ENTRYP without regard to a state of the initial precharge signalPCGPS. The refresh signal generator 700B includes a second NOR gate NOR2and a seventh inverter INV7. The second NOR gate NOR2 logically combinesthe reset exit signal RST_EXITP and the initial refresh signal REFPS.The seventh inverter INV7 inverts an output of the second NOR gate NOR2and outputs the refresh signal REFP. The refresh signal REFP isactivated in response to an activation of the reset exit signalRST_EXITP without regard to a state of the initial refresh signal REFPS.

As above described, the present invention detects a starting timing anda termination timing of the reset operation by using the reset statesignal generator 600 and controls a refresh operation and a prechargeoperation in response to the reset operation by using the resetcontroller 700. Therefore, the present invention provides a betterperformance compared with the conventional art which does not includinga circuit for controlling its operation in response to the resetoperation.

In the abovementioned embodiment, the logic circuits used in the resetstate signal generator 600 and the reset controller 700 are arranged forinput and output signals which are activated as a logic high level.Alternatively, the internal circuitry of the present invention can bechanged in accordance with an active logic level of the input and outputsignals. In addition, the present invention can be implemented with anykind of circuitry which performs a precharge operation in response to astarting timing of the reset operation and performs a refresh operationin response to a termination timing of the reset operation. Furthermore,the reset controller of the present invention can be implemented to onlycontrol the refresh operation because the precharge operation isautomatically performed while performing the refresh operation.

The present invention includes a reset control circuit for controllingan operation of a semiconductor memory device in response to a resetoperation of a system using the semiconductor memory device. Therefore,it is possible for the present invention to improve the reliability andstability of the operation of the semiconductor memory device itself andthe system including it.

The present application contains subject matter related to Korean patentapplication Nos. 2005-90914 and 2006-49002, filed in the Korean PatentOffice on Sep. 29, 2005 and on May 30, 2006, the entire contents ofwhich is incorporated herein by reference.

While the present invention has been described with respect to theparticular embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1. A semiconductor memory device, comprising: a reset signal generatorfor generating a reset entry signal and a reset exit signal respectivelyin response to a start timing and a termination timing of a resetoperation of the system; and a reset controller for performing aprecharge operation in response to the reset entry signal and a refreshoperation in response to the reset exit signal.
 2. The semiconductormemory device as recited in claim 1, wherein the reset signal generatorincludes: an input buffer for receiving a reset enable signal preventinga data access during a predetermined period; and a reset state signalgenerator for generating the reset entry signal and the reset exitsignal in response to an output of the input buffer.
 3. Thesemiconductor memory device as recited in claim 2, wherein the resetstate signal generator includes: a reset entry signal generator forgenerating the reset entry signal; and a reset exit signal generator forgenerating the reset exit signal.
 4. The semiconductor memory device asrecited in claim 3, wherein the reset entry signal generator includes: afirst inverter for inverting the output of the input buffer; a delay fordelaying an output of the first inverter; a second inverter forinverting an output of the delay; a NAND gate for logically combiningthe output of the first inverter and an output of the second inverter;and a third inverter for inverting an output of the NAND gate to therebyoutput the reset entry signal.
 5. The semiconductor memory device asrecited in claim 3, wherein the reset exit signal generator includes: adelay for delaying the output of the input buffer; a first inverter forinverting an output of the delay; a NAND gate for logically combiningthe output of the delay and an output of the first inverter; and asecond inverter for inverting an output of the NAND gate to therebyoutput the reset exit signal.
 6. The semiconductor memory device asrecited in claim 1, wherein the reset controller includes: a prechargesignal generator for generating a precharge signal used for theprecharge operation; and a refresh signal generator for generating arefresh signal used for the refresh operation.
 7. The semiconductormemory device as recited in claim 6, wherein the precharge signalgenerator includes: a first NOR gate for logically combining the resetentry signal and an initial precharge signal; and a first inverter forinverting an output of the first NOR gate to thereby output theprecharge signal, wherein the initial precharge signal is generated bydecoding external control signals.
 8. The semiconductor memory device asrecited in claim 7, wherein the refresh signal generator includes: asecond NOR gate for logically combining the reset exit signal and aninitial refresh signal; and a second inverter for inverting an output ofthe second NOR gate to thereby output the refresh signal, wherein theinitial refresh signal is generated by decoding the external controlsignals.
 9. A semiconductor memory device, comprising: a command decoderfor decoding input commands; a control signal generator for generatingcontrol signals for a data access based on outputs of the commanddecoder; and a reset block for preventing the data access and performinga precharge operation and a refresh operation in response to a resetsignal.
 10. The semiconductor memory device as recited in claim 9,wherein the reset block includes: an input buffer for receiving a resetenable signal preventing a data access during a predetermined period;and a reset state signal generator for generating the reset entry signaland the reset exit signal in response to an output of the input buffer.11. The semiconductor memory device as recited in claim 10, wherein thereset state signal generator includes: a reset entry signal generatorfor generating the reset entry signal; and a reset exit signal generatorfor generating the reset exit signal.
 12. The semiconductor memorydevice as recited in claim 11, wherein the reset entry signal generatorincludes: a first inverter for inverting the output of the input buffer;a delay for delaying an output of the first inverter; a second inverterfor inverting an output of the delay; a NAND gate for logicallycombining the output of the first inverter and an output of the secondinverter; and a third inverter for inverting an output of the NAND gateto thereby output the reset entry signal.
 13. The semiconductor memorydevice as recited in claim 11, wherein the reset exit signal generatorincludes: a delay for delaying the output of the input buffer; a firstinverter for inverting an output of the delay; a NAND gate for logicallycombining the output of the delay and an output of the first inverter;and a second inverter for inverting an output of the NAND gate tothereby output the reset exit signal.
 14. The semiconductor memorydevice as recited in claim 9, wherein the control signal generatorincludes: a reset controller for prechargeing a precharge signal inresponse to the reset entry signal and a refresh signal in response tothe reset exit signal; a self precharge unit for generating a selfprecharge enable signal based on the refresh signal; and a row addressstrobe (RAS) signal generator for generating a RAS signal in response tothe precharge signal, the refresh signal and the self precharge enablesignal.
 15. The semiconductor memory device as recited in claim 14,wherein the reset controller includes: a precharge signal generator forgenerating a precharge signal used for the precharge operation; and arefresh signal generator for generating a refresh signal used for therefresh operation.
 16. The semiconductor memory device as recited inclaim 15, wherein the precharge signal generator includes: a first NORgate for logically combining the reset entry signal and an initialprecharge signal; and a first inverter for inverting an output of thefirst NOR gate to thereby output the precharge signal, wherein theinitial precharge signal is generated by decoding external controlsignals.
 17. The semiconductor memory device as recited in claim 16,wherein the refresh signal generator includes: a second NOR gate forlogically combining the reset exit signal and an initial refresh signal;and a second inverter for inverting an output of the second NOR gate tothereby output the refresh signal, wherein the initial refresh signal isgenerated by decoding the external control signals.
 18. Thesemiconductor memory device as recited in claim 9, wherein the commanddecoder performs a decoding of addresses and commands relating to a rowdata access.